Senior Soc Timing Engineer

Indclutch

Penang, Malaysia
On-site
Static timing analysis
Interface timing constraints
Timing convergence analysis
Indclutch is seeking a Senior SOC Timing Engineer in Penang, Malaysia, responsible for timing closure and signoff of FPGA/SoC and subsystem timing. The ideal candidate will possess extensive experience in static timing analysis and proficiency in physical design EDA tools

Job Summary

  • As an SOC Timing engineer candidate will be responsible for timing closure and signoff of FPGA/SoC and Subsystem timing.
  • Candidate will be involved in static timing analysis, providing/deriving interface timing constraints to partitions and doing final timing signoff.
  • Candidate will also work closely with design and architecture team for timing convergence analysis and will also work with physical design team for timing closure.

Matching Summary

Match Score: 85

Indclutch is seeking a Senior SOC Timing Engineer in Penang, Malaysia, responsible for timing closure and signoff of FPGA/SoC and subsystem timing. The ideal candidate will possess extensive experience in static timing analysis and proficiency in physical design EDA tools.

Skills & Requirements

Must-have

  • Static timing analysis
  • Interface timing constraints
  • Timing convergence analysis
  • Timing closure
  • Primetime/PTPX
  • TCL
  • Python

Nice-to-have

  • Problem solving skills
  • Analytical skills
  • Communication skills

Key Requirements

  • 7+ Years’ experience
  • BE/MS/Phd in Electronics/Electrical Engineering
  • Experience in timing signoff in 10nm or lower technology

Work Rights

Not specified

Tailored Resume

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