Validates and researches Quartus Synthesis & Compiler optimizations, Partial Reconfiguration (PR) flow, and Debugging features using Altera FPGA Hardware and Quartus Design Software
Job Summary
Validates and researches Quartus Synthesis & Compiler optimizations, Partial Reconfiguration (PR) flow, and Debugging features using Altera FPGA Hardware and Quartus Design Software.
Creates device-specific testcases with Verilog/VHDL and Altera IPs, verifying timing and functionality using industry-standard tools, and regressing designs for QoR.
Collaborates with cross-functional teams to enhance Synthesis & Compiler test coverage and resolve customer issues.
Matching Summary
Validates and researches Quartus Synthesis & Compiler optimizations, Partial Reconfiguration (PR) flow, and Debugging features using Altera FPGA Hardware and Quartus Design Software.
Skills & Requirements
Must-have
FPGA RTL Design
VHDL, Verilog, SystemVerilog
Altera Quartus
Xilinx Vivado
Partial Reconfiguration (PR) flow
SignalTap or ChipScope
VCS, Questa, XCelium simulation
Timing Analysis (STA)
Shell, Perl, TCL or Python Scripting
Nice-to-have
cross-functional team collaboration
customer issue resolution
performance monitoring
design test coverage improvement
Key Requirements
Min. 5+ years of relevant experience
Master's/Bachelor's Degree in Electronics/VLSI/Digital Design
FPGA/ASIC RTL Design, verification and HW Debug experience