Validates and researches Compiler optimizations, Partial Reconfiguration (PR) flow, and Debugging features using Quartus Design Software and Altera FPGA Hardware
Job Summary
Validates and researches Compiler optimizations, Partial Reconfiguration (PR) flow, and Debugging features using Quartus Design Software and Altera FPGA Hardware.
Leads the Partial Reconfiguration (PR) Validation team and creates designs using HDLs and Altera IPs, verifying them for functionality and timing.
Collaborates with cross-functional teams to develop and improve validation strategies and help resolve customer issues.
Matching Summary
Validates and researches Compiler optimizations, Partial Reconfiguration (PR) flow, and Debugging features using Quartus Design Software and Altera FPGA Hardware.
Skills & Requirements
Must-have
FPGA Partial Reconfiguration (PR) flow
Altera FPGA Hardware
Quartus Design Software
RTL design and verification
SignalTap or ChipScope
Shell, Perl/TCL or Python Scripting
Nice-to-have
Compiler optimizations validation
cross-functional team collaboration
customer issue resolution
Key Requirements
6+ years of relevant experience
Master's/Bachelor's Degree
FPGA Devices like Agilex, Virtex
Simulation/Verification using VCS, Questa, XCelium