You will be responsible for leading the design analysis and methodologies of the different types of memory blocks and data path subsystems
Job Summary
You will be responsible for leading the design analysis and methodologies of the different types of memory blocks and data path subsystems.
Responsible for methodology enablement for memory blocks to meet over 5GHz Freq and low-power digital designs with optimal area.
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
Matching Summary
You will be responsible for leading the design analysis and methodologies of the different types of memory blocks and data path subsystems.
Skills & Requirements
Must-have
memory block design
data path subsystems
Static timing analysis
back-end design implementation
statistical variation understanding
Nice-to-have
high speed low power digital design
Verilog familiarity
Tcl Perl Python scripting
spice simulations and analysis
Key Requirements
Masters Degree in Electrical or Computer Engineering with 8+ years of experience
Bachelors Degree with 10+ years of experience
Technical Expertise in synthesis, P and R tools preferred