Mixed Signal Logic Verification Engineer

Intel Corporation

Bangalore, India
Hybrid
11-15 years asic soc verification experience
Expert system verilog uvm testbench architecture
Mixed signal ip verification strategy
This role drives complex SoC/ASIC verification for mixed signal IPs requiring 11-15 years of industry experience

Job Summary

  • This role drives complex SoC/ASIC verification for mixed signal IPs requiring 11-15 years of industry experience.
  • The engineer will design advanced test benches using System Verilog and UVM while leading verification plans and methodologies.
  • Candidates must possess strong debugging capabilities including post-silicon failure analysis and formal verification techniques.

Matching Summary

This role drives complex SoC/ASIC verification for mixed signal IPs requiring 11-15 years of industry experience.

Skills & Requirements

Must-have

  • 11-15 years ASIC SoC verification experience
  • Expert System Verilog UVM testbench architecture
  • Mixed signal IP verification strategy
  • Post-silicon debug and RTL analysis
  • Formal verification model checking methods
  • JTAG APB protocol proficiency

Nice-to-have

  • Mentoring junior engineers
  • Code review leadership
  • Python Perl Tcl scripting skills
  • Collaboration with architects
  • Coverage closure improvement

Key Requirements

  • 11-15 years of ASIC/SoC verification experience
  • B.E/B.Tech or M.E/M.Tech/MS in Electronics/VLSI Engineering
  • Hands-on experience with Synopsys VCS Cadence Xcelium tools

Work Rights

Not specified

Tailored Resume

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