Lead Design Engineer - Physical Design

Cadence

High-speed digital ddr and hbm ip implementation
Floorplan, cts, sta, and physical verification
Scripting skills in perl, tcl, python, or c shell
The role focuses on high-speed digital DDR and HBM IP physical implementation within a team delivering advanced technology products

Job Summary

  • The role focuses on high-speed digital DDR and HBM IP physical implementation within a team delivering advanced technology products.
  • Candidates will solve complex design issues and develop scripts to enhance the current physical design flow.
  • The position requires analyzing PPA optimization results to implement optimal design parameters across various projects.

Matching Summary

The role focuses on high-speed digital DDR and HBM IP physical implementation within a team delivering advanced technology products.

Skills & Requirements

Must-have

  • High-speed digital DDR and HBM IP implementation
  • Floorplan, CTS, STA, and physical verification
  • Scripting skills in Perl, TCL, Python, or C shell

Nice-to-have

  • PPA optimization methodology experience
  • Advanced process node knowledge (3nm/5nm)
  • Tool development and flow enhancement

Key Requirements

  • MS in EE with at least 3 years relevant IC design experience
  • Solid background in circuits, electronics, and physics
  • Familiarity with EDA tools like Innovus, ICC, Calibre, Tempus, PrimeTime

Work Rights

Not specified

Tailored Resume

Cover Letter