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Cisco is seeking a Sta CAD/Methodology Engineer to join their Silicon One Team in Yerevan, Armenia, focusing on silicon architecture and ASIC design. The role emphasizes developing Static Timing Analysis (STA) flows and automation, with a strong collaborative culture and opportunities for innovation.
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Job Summary
This hybrid role involves leading the development of scalable Static Timing Analysis flows and automation for Cisco's Silicon One team.
The engineer will collaborate with RTL, DFT, and physical design teams to support timing closure and debug complex chip partitions.
Candidates will contribute to defining innovative Physical Design methodologies and creating robust flows for advanced process nodes.
Matching Summary
Match Score: 75
**
Cisco is seeking a Sta CAD/Methodology Engineer to join their Silicon One Team in Yerevan, Armenia, focusing on silicon architecture and ASIC design. The role emphasizes developing Static Timing Analysis (STA) flows and automation, with a strong collaborative culture and opportunities for innovation.
**
Skills & Requirements
Must-have
4+ years ASIC or SoC design experience
PrimeTime or Tempus timing tool proficiency
TCL and Python scripting expertise
STA fundamentals including setup/hold analysis
SDC constraint development and validation
Nice-to-have
Experience with large-scale networking SoCs
Familiarity with Unix/Linux development environments
Knowledge of EDA tool job scheduling systems
Version control system experience like Git or Perforce
Background in physical design flows and synthesis
Key Requirements
Bachelor's or Master's degree in Electrical or Computer Engineering
Minimum 4 years of experience in STA, CAD automation, or physical design methodology