Senior Ic Verification Engineer

Broadcom

Multiple Locations
Base: $127,100 - $203,400; bonus/equity: discretio...
Systemverilog and uvm verification
Hdl languages verilog/vhdl
Constrained random environment design
The engineer will be responsible for advanced verification tasks including environment development, coverage implementation, and debugging simulation failures

Job Summary

  • The engineer will be responsible for advanced verification tasks including environment development, coverage implementation, and debugging simulation failures.
  • Broadcom offers a competitive and comprehensive benefits package including medical, dental, vision, 401(K) with company matching, ESPP, and paid leave.
  • Broadcom is an equal opportunity employer considering qualified applicants without regard to protected characteristics and supports applicants with arrest and conviction records consistent with local law.

Matching Summary

The engineer will be responsible for advanced verification tasks including environment development, coverage implementation, and debugging simulation failures.

Salary

Base: $127,100 - $203,400; Bonus/Equity: Discretionary annual bonus and equity awards; Benefits: Medical, dental, vision, 401(K) matching, ESPP, paid leave

Skills & Requirements

Must-have

  • SystemVerilog and UVM verification
  • HDL languages Verilog/VHDL
  • Constrained random environment design
  • HDL simulator debugging
  • Subsystem level verification

Nice-to-have

  • Excellent communication skills
  • Leadership skills
  • Object oriented programming knowledge
  • Critical thinking for engineering problems
  • Matrix organization communication

Key Requirements

  • Bachelors in EE, CE, or CS with 12+ years experience
  • Masters degree in EE, CE, or CS with 10+ years experience
  • Legal authorization to work in the US

Work Rights

Must have legal authorization to work in the US

Tailored Resume

Cover Letter