Principal Dft Engineer

NXP USA INC.

Not specified; not specified; not specified
10+ years industry experience in soc dft
Scan insertion and architecture implementation
Atpg pattern generation for fault coverage
The role involves architecting and validating in-vehicle networking devices as part of NXP's Automotive grade products

Job Summary

  • The role involves architecting and validating in-vehicle networking devices as part of NXP's Automotive grade products.
  • Candidates will lead the integration of digital subsystems and ensure high fault coverage through advanced ATPG patterns.
  • Success requires driving post-silicon validation to root cause failures and improve manufacturing test efficiency.

Matching Summary

The role involves architecting and validating in-vehicle networking devices as part of NXP's Automotive grade products.

Salary

Not specified; Not specified; Not specified

Skills & Requirements

Must-have

  • 10+ years industry experience in SoC DFT
  • Scan insertion and architecture implementation
  • ATPG pattern generation for fault coverage
  • MBIST and LBIST integration expertise
  • STA timing closure and SDC constraints
  • Silicon bring-up and post-silicon debug
  • Proficiency with Tessent or Synopsys tools

Nice-to-have

  • Strong Verilog/SystemVerilog HDL skills
  • Tcl/Python automation scripting abilities
  • Experience with test compression techniques
  • Collaboration with physical design teams
  • Gate-level simulation verification skills

Key Requirements

  • B.S./M.S. Electrical or Computer Engineering degree
  • Minimum 10 years of SoC DFT experience
  • Expertise in Mentor Graphics Tessent or Synopsys tools

Work Rights

Not specified

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