Marvell is seeking a senior to staff design verification engineer to join their Custom Silicon Engineering Team, focusing on verification for read channel storage IP designs within the semiconductor industry. The ideal candidate will have a strong background in digital design and verification methodologies, along with proficiency in relevant programming and verification languages
Job Summary
This role involves developing verification plans for read channel storage IP designs within Marvell's Custom Silicon Engineering Team.
Candidates will utilize industry-standard tools like SystemVerilog and UVM to perform functional and performance verification of complex digital designs.
The position offers competitive compensation including a 13th-month salary, performance-based bonus, RSUs, and premium health insurance.
Matching Summary
Match Score: 85
Marvell is seeking a senior to staff design verification engineer to join their Custom Silicon Engineering Team, focusing on verification for read channel storage IP designs within the semiconductor industry. The ideal candidate will have a strong background in digital design and verification methodologies, along with proficiency in relevant programming and verification languages.
Salary
Competitive salary; 13th-month salary and performance-based bonus; RSUs for new joiners
Skills & Requirements
Must-have
SystemVerilog and UVM proficiency
ASIC design flow understanding
Digital Signal Processing knowledge
C/C++ DSP modeling experience
EDA tools expertise (Cadence/Synopsys)
Python or Perl scripting skills
Nice-to-have
Mentoring junior verification engineers
Strong mathematical problem-solving
Excellent English communication skills
Experience with custom SoC design
Collaboration with architecture teams
Key Requirements
BS/MS/PhD in Electrical or Computer Engineering
Eligibility for US export control access
Fluent English language proficiency
Work Rights
Must be eligible to access export-controlled information under US law