Design Verification Manager

Altera

Penang, Malaysia
Onsite
Bs/ms/phd in electrical or computer science engineering
15+ years technical experience in pre silicon validation
Expertise in ovm/uvm and system verilog
Altera is seeking a Design Verification Manager in Penang, Malaysia, to lead a team of design verification engineers in the verification of IP and SoC designs. The role requires extensive technical experience and expertise in verification methodologies, with a focus on enhancing security within the verification processes

Job Summary

  • The role involves directing and managing a team of design verification engineers responsible for IP and SoC design verification.
  • Candidates must deploy and manage leading silicon design verification processes based on the latest industry best practices.
  • The position requires collaboration with program leaders to meet verification delivery metrics and incorporate security-related testing.

Matching Summary

Match Score: 85

Altera is seeking a Design Verification Manager in Penang, Malaysia, to lead a team of design verification engineers in the verification of IP and SoC designs. The role requires extensive technical experience and expertise in verification methodologies, with a focus on enhancing security within the verification processes.

Skills & Requirements

Must-have

  • BS/MS/PhD in Electrical or Computer Science Engineering
  • 15+ years technical experience in Pre Silicon Validation
  • Expertise in OVM/UVM and System Verilog
  • Experience with constrained random verification methodologies
  • Knowledge of TCL/PERL/Python scripting

Nice-to-have

  • Formal verification experience
  • Experience with Ethernet PCIe MACSEC IPSEC protocols
  • FPGA architecture or FPGA prototyping experience
  • SME/team management or Technical Lead background
  • Security milestone expectations understanding

Key Requirements

  • BS MS or PhD in Electrical or Computer Science Engineering
  • 15+ years of technical experience
  • Pre Silicon Validation/Verification expertise
  • OVM UVM System Verilog proficiency
  • Constrained random verification methodologies

Work Rights

Not specified

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