Senior Digital Verification Engineer

NXP Semiconductors

Pune, India
Systemverilog and uvm
Asic/ip verification experience
Test planning and execution
Implement and execute verification for IP blocks and sub-systems using SystemVerilog and UVM, following established verification methodologies and plans

Job Summary

  • Implement and execute verification for IP blocks and sub-systems using SystemVerilog and UVM, following established verification methodologies and plans.
  • Contribute to verification closure, analyzing coverage results, identifying gaps, and adding tests or coverage points to meet sign-off requirements.
  • Work closely with peers and senior engineers, contribute to team deliverables and continuously improving verification quality.

Matching Summary

Implement and execute verification for IP blocks and sub-systems using SystemVerilog and UVM, following established verification methodologies and plans.

Skills & Requirements

Must-have

  • SystemVerilog and UVM
  • ASIC/IP verification experience
  • Test planning and execution
  • Functional and code coverage
  • RTL issue debugging
  • Version control and issue-tracking tools

Nice-to-have

  • Low-power verification concepts
  • HW-FW co-verification
  • Problem-solving skills
  • Attention to detail
  • Willingness to learn

Key Requirements

  • 6 to 10 years of industry experience
  • At least one or more tape-out cycles
  • Proficiency in SystemVerilog and UVM
  • Exposure to C/C++ programming
  • Basic scripting skills (Python, Perl, or similar)
  • Effective written and verbal communication skills

Work Rights

Not specified

Tailored Resume

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