Sr Principal Design Engineer

Cadence

Noida, India
Memory controller dv group management
Constrained random functional verification
Formal property verification
The role requires the management of a Memory Controller DV group focusing on MDV verification including Constrained Random Functional Verification, Formal Property Verification, project DV status and execution, and mentorship of junior engineers

Job Summary

  • The role requires the management of a Memory Controller DV group focusing on MDV verification including Constrained Random Functional Verification, Formal Property Verification, project DV status and execution, and mentorship of junior engineers.
  • Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
  • The role will require customer interactions including pre and post-sales activities, DV methodology review and customer support.

Matching Summary

The role requires the management of a Memory Controller DV group focusing on MDV verification including Constrained Random Functional Verification, Formal Property Verification, project DV status and execution, and mentorship of junior engineers.

Skills & Requirements

Must-have

  • Memory Controller DV group management
  • Constrained Random Functional Verification
  • Formal Property Verification
  • Verilog, SV with UVM methodology
  • AXI and/or CHI experience
  • DDR, PCIe, UCIe or USB expertise

Nice-to-have

  • Creative problem solving
  • Integrity and collaboration
  • Continuous learning and development
  • Customer-facing interactions

Key Requirements

  • 11+ years of relevant experience
  • Functional verification fundamentals
  • Environment planning and development
  • Test plan generation
  • BE/BTech/ME/MS/MTech in Electrical/Electronics or equivalent

Work Rights

Not specified

Tailored Resume

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