Senior Design Verification Engineer

Altera

San Jose, California, United States
Base: $142.6k - $206.5k usd (bay area); bonus/equi...
System verilog uvm environment development
Ethernet pcie cxl protocol verification
Complex coverage driven random constraint testing
The role involves leading the verification and validation of next-generation High-Speed Protocol IP across Altera's FPGA product portfolios

Job Summary

  • The role involves leading the verification and validation of next-generation High-Speed Protocol IP across Altera's FPGA product portfolios.
  • Candidates must develop comprehensive test plans, create directed and random test cases, and achieve strict coverage metrics using System Verilog and UVM.
  • The position requires collaborating with cross-functional teams to support IP functional validation tests on actual FPGA development kits.

Matching Summary

The role involves leading the verification and validation of next-generation High-Speed Protocol IP across Altera's FPGA product portfolios.

Salary

Base: $142.6k - $206.5k USD (Bay Area); Bonus/Equity: Incentive opportunities available; Benefits: Not specified

Skills & Requirements

Must-have

  • System Verilog UVM environment development
  • Ethernet PCIe CXL protocol verification
  • Complex coverage driven random constraint testing
  • RTL design debugging and isolation
  • FPGA hardware bring-up and validation

Nice-to-have

  • Cross-functional team collaboration skills
  • Verification tool and flow development
  • Advanced productivity improvement techniques

Key Requirements

  • BS/MS in Electrical or Computer Engineering
  • 9+ years industry experience in verification collateral
  • 7+ years experience with Ethernet/PCIe/CXL protocols
  • 7+ years fluency in UVM and complex environments
  • Eligibility for US export authorizations

Work Rights

Must be eligible for required US export authorizations

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