Asic Verification Engineer

Cisco

Egypt
System verilog and uvm methodology
Functional coverage and constrained random dv
Asic verification across simulation and emulation
Join the Cisco Common ASIC Group, a team responsible for developing ASICs at the heart of Cisco's next-generation switching systems

Job Summary

  • Join the Cisco Common ASIC Group, a team responsible for developing ASICs at the heart of Cisco's next-generation switching systems.
  • As an ASIC Verification Engineer, you will develop and upgrade test benches, collaborate with design and hardware teams, and contribute to verification infrastructure.
  • Cisco offers a collaborative team environment with opportunities to innovate and grow within a global technology leader.

Matching Summary

Join the Cisco Common ASIC Group, a team responsible for developing ASICs at the heart of Cisco's next-generation switching systems.

Skills & Requirements

Must-have

  • System Verilog and UVM methodology
  • Functional coverage and constrained random DV
  • ASIC verification across simulation and emulation
  • Testbench development and maintenance
  • Debugging and regression testing

Nice-to-have

  • Python, Perl, shell scripting
  • C, C++ programming and debugging
  • Collaborative and team-focused mindset
  • Good written and verbal communication skills
  • Strong drive to learn and grow

Key Requirements

  • Master’s degree in Electrical & Electronics or Computer Engineering
  • 2 to 3 years experience in Design Verification
  • Ability to debug issues independently
  • Experience with functional coverage and constrained random DV
  • Not specified work authorization

Work Rights

Not specified

Tailored Resume

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