Sr Principal Design Engineer

Cadence

Rtl design using verilog
Systemverilog experience required
Uvm based environment usage and debugging
The role involves designing and supporting the RTL for the DDR Memory Controller solution at Cadence

Job Summary

  • The role involves designing and supporting the RTL for the DDR Memory Controller solution at Cadence.
  • Candidates must ensure designs are clean for LINT and CDC guidelines while supporting various customer configurations.
  • The position requires expertise in leading DDR memory protocols including DDR4 and LPDDR4.

Matching Summary

The role involves designing and supporting the RTL for the DDR Memory Controller solution at Cadence.

Skills & Requirements

Must-have

  • RTL design using Verilog
  • SystemVerilog experience required
  • UVM based environment usage and debugging

Nice-to-have

  • AXI3/4 protocol experience desired
  • DDR Memory controller protocol knowledge
  • Prior IP development team experience

Key Requirements

  • BE/B.Tech/ME/M.Tech in Electrical, Electronics, or VLSI
  • Experience as a design and verification engineer
  • Large portion of recent work on RTL design and development

Work Rights

Not specified

Tailored Resume

Cover Letter