As a member of the PMC Logic Design Verification team, you will work closely with IP architects to define and develop verification testbench and building RTL models for verification
Job Summary
As a member of the PMC Logic Design Verification team, you will work closely with IP architects to define and develop verification testbench and building RTL models for verification.
You will be validating and verifying the functionality of new architectural features of next generation designs by developing testplan, tests content or test tools.
Your expertise will grow as you debug and resolve issues on system platforms using software and RTL simulation tools.
Matching Summary
As a member of the PMC Logic Design Verification team, you will work closely with IP architects to define and develop verification testbench and building RTL models for verification.
Skills & Requirements
Must-have
UVM and System Verilog
RTL models for verification
developing testplan, tests content
debug and resolve issues
Power Management Controller IP
Nice-to-have
strong influencing skills
creative in problem solving
motivated, self-driven and independent
Hardware-Firmware co-validation
Knowledge of Agile
Key Requirements
Bachelor's, Master's, or Ph.D. in Electronics Engineering, Computer Engineering, or equivalent
At least 8 years of relevant working experience
Familiarize with UVM Verification Components
Strong in analysis, debugging skills
Working in Assembly language, embedded firmware, RTOS, BIOS