Research Fellow / Research Engineer (Secure FPGA Design and Verification)

TUM CREATE LIMITED

Singapore, Singapore
Competitive salary commensurate with experience; m...
Not specified (potentially hybrid or onsite based on research collaboration)
Fpga design flows
Risc-v architecture knowledge
Rtl digital design skills
TUM CREATE is seeking a Research Fellow / Research Engineer for its QUASAR project, focusing on secure FPGA design and verification using RISC-V platforms. The position is ideal for recent graduates with a background in electrical engineering or computer science, emphasizing hands-on experience with digital design and FPGA systems

Job Summary

  • This role focuses on implementing Post-Quantum Cryptography within the RISC-V ecosystem for the QUASAR project.
  • Candidates will support the deployment of CVA6-based SoC systems on FPGA platforms and debug system-level issues.
  • The position offers hands-on experience with state-of-the-art open-source RISC-V cores in a collaborative international research environment.

Matching Summary

Match Score: 85

TUM CREATE is seeking a Research Fellow / Research Engineer for its QUASAR project, focusing on secure FPGA design and verification using RISC-V platforms. The position is ideal for recent graduates with a background in electrical engineering or computer science, emphasizing hands-on experience with digital design and FPGA systems.

Salary

Competitive salary commensurate with experience; Medical insurance included; Good amount of leave/vacation days

Skills & Requirements

Must-have

  • FPGA design flows
  • RISC-V architecture knowledge
  • RTL digital design skills
  • Python or C/C++ programming
  • System bring-up and validation

Nice-to-have

  • Hardware verification methodologies
  • Linux-based embedded systems
  • Side-channel resistance analysis
  • Open-source hardware platforms
  • Vivado tool flow experience

Key Requirements

  • Degree in Electrical, Computer Engineering, or Computer Science
  • Strong foundation in digital design and timing
  • Hands-on experience with FPGA design flows

Work Rights

Not specified

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