Asic Design Hardware Engineer - Sdc/sta (hybrid)

Cisco UK

San Jose, California, United States
Base: $165,000.00 to $241,400.00; bonus/equity: el...
Onsite
6+ years asic experience
Synopsys primetime sta tool proficiency
Sdc/sta constraint development
Join the Cisco Silicon One team to develop unified silicon architecture for web scale networks

Job Summary

  • Join the Cisco Silicon One team to develop unified silicon architecture for web scale networks.
  • You will develop timing constraints at block and full-chip levels using industry-standard tools like TCM and Timevision.
  • The role offers a unique blend of large organization resources with startup culture and growth opportunities.

Matching Summary

Join the Cisco Silicon One team to develop unified silicon architecture for web scale networks.

Salary

Base: $165,000.00 to $241,400.00; Bonus/Equity: Eligible for annual bonuses and RSUs; Benefits: Medical, dental, vision, 401(k), paid time off

Skills & Requirements

Must-have

  • 6+ years ASIC experience
  • Synopsys Primetime STA tool proficiency
  • SDC/STA constraint development
  • TCL scripting expertise
  • Verilog/SystemVerilog knowledge

Nice-to-have

  • Strong documentation skills
  • Cross-functional collaboration
  • Innovative problem-solving mindset
  • Block-level RTL design experience
  • IP integration capabilities

Key Requirements

  • Bachelor's in ECE with 6+ years ASIC experience
  • Master's in ECE with 4+ years ASIC experience
  • Experience with Synopsys DC/DCG/FC synthesis tools
  • Knowledge of clocking, timing exceptions, and async boundaries

Work Rights

Must live within commuting distance of San Jose, CA office

Tailored Resume

Cover Letter