Responsible for carrying out design validation for Altera next generation IP's across the Altera FPGA IP product portfolios
Job Summary
Responsible for carrying out design validation for Altera next generation IP's across the Altera FPGA IP product portfolios.
Create comprehensive verification and validation plan based on IP/FPGA architecture specifications and carry out all the IP validation tasks.
Drive system test design implementation and overall IP system validation on HW, maximizing FPGA hardware capability to bring substantial improvement to IP quality & usability.
Matching Summary
Responsible for carrying out design validation for Altera next generation IP's across the Altera FPGA IP product portfolios.
Salary
$142.6k - $206.5k USD
Skills & Requirements
Must-have
High-Speed Protocol IP verification
FPGA IP product portfolios
System Verilog and UVM
coverage driven random constraint UVM environments
IP bring-up on actual FPGA development kits
Nice-to-have
advanced verification techniques
cross-functional team collaboration
maximize FPGA hardware capability
Key Requirements
BS/MS in Electrical Engineering, Computer Engineering or related field
9+ years of industry experience
9+ years of experience developing verification collateral in Verilog, System Verilog and UVM
7+ years with Ethernet/PCIe/CXL protocol verification
7+ years in UVM Fluency
7+ years of complex coverage driven random constraint UVM environments
7+ years of experience with High level Specification into test plan and developing tests cases