Asic Design Verification Engineer Ii (intern) - United States

Cisco

Multiple Locations, United States
Base: $44,000.00 - $185,000.00; bonus/equity: not ...
Knowledge of object-oriented verification methodologies
Develop detailed and comprehensive test plans
Knowledge of systemverilog/uvm
The ASIC Design Verification Intern Engineer will be a member of a team working on next generation 100G-1T coherent optical communications products

Job Summary

  • The ASIC Design Verification Intern Engineer will be a member of a team working on next generation 100G-1T coherent optical communications products.
  • This role is focused on verifying highly-complex ASICs that are used in next-generation telecom systems.
  • A successful candidate will be energetic, collaborative and passionate about learning how to deliver the most advanced high speed optical products in the world.

Matching Summary

The ASIC Design Verification Intern Engineer will be a member of a team working on next generation 100G-1T coherent optical communications products.

Salary

Base: $44,000.00 - $185,000.00; Bonus/Equity: Not specified; Benefits: Medical, dental and vision insurance

Skills & Requirements

Must-have

  • knowledge of object-oriented verification methodologies
  • develop detailed and comprehensive test plans
  • knowledge of SystemVerilog/UVM

Nice-to-have

  • knowledge of DSP algorithms
  • lab silicon validation experience
  • excellent communication skills

Key Requirements

  • currently enrolled in a graduate degree program
  • knowledge of C and/or C++

Work Rights

Not specified

Tailored Resume

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