Design Verification Engineer

Altera

San Jose, California, United States
Base: $142.6k - $206.5k usd (bay area); bonus/equi...
Uvm-based testbench development
Pcie gen4/gen5/gen6 protocol verification
Systemverilog assertion writing
This senior role focuses on verifying the correctness, performance, and compliance of next-generation FPGA and SoC designs with a strong emphasis on PCIe subsystems

Job Summary

  • This senior role focuses on verifying the correctness, performance, and compliance of next-generation FPGA and SoC designs with a strong emphasis on PCIe subsystems.
  • The successful candidate will develop comprehensive UVM-based testbenches and execute advanced simulation and formal techniques to ensure complete specification coverage.
  • As an independent company, Altera empowers its teams to drive breakthrough innovation and shape the future of the FPGA industry across rapidly evolving markets like AI and cloud.

Matching Summary

This senior role focuses on verifying the correctness, performance, and compliance of next-generation FPGA and SoC designs with a strong emphasis on PCIe subsystems.

Salary

Base: $142.6K - $206.5K USD (Bay Area); Bonus/Equity: Incentive opportunities available; Benefits: Not specified

Skills & Requirements

Must-have

  • UVM-based testbench development
  • PCIe Gen4/Gen5/Gen6 protocol verification
  • SystemVerilog assertion writing
  • Constrained-random test scenarios
  • Formal property verification

Nice-to-have

  • CXL 2.0/3.0 protocol knowledge
  • FPGA architecture expertise
  • Mentoring junior engineers
  • Reusable verification IP development

Key Requirements

  • Bachelor's degree in Electrical or Computer Engineering
  • 8+ years of professional Design Verification experience
  • 4+ years verifying PCIe IP including Gen4 or later
  • 7+ years writing SystemVerilog and UVM testbenches
  • Eligible for required U.S. export authorizations

Work Rights

Must be eligible for required U.S. export authorizations

Tailored Resume

Cover Letter