Sr. Soc Design Verification Engineer

Altera Corporation

Bengaluru, Karnataka, India
Uvm methodology
System verilog language
Linux/unix scripting
You will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology

Job Summary

  • You will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology.
  • Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage verification plan.
  • Experience on Emulation will be an add on.

Matching Summary

You will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology.

Skills & Requirements

Must-have

  • UVM methodology
  • System Verilog language
  • Linux/Unix scripting
  • Perl and/or Python proficiency
  • Pre-silicon system verification
  • FPGA & Full Chip design verification

Nice-to-have

  • Emulation experience
  • ARM and RISC Debug Architectures
  • UltraSoC/Tessent Embedded Analytics Debug Architecture
  • work with team spread across different geography sites
  • Flexible in dynamic environment

Key Requirements

  • 10+ years of experience
  • complex ASIC designs and/or verification
  • Design for Debug architecture and design verification
  • Formal verification method

Work Rights

Not specified

Tailored Resume

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