Performs functional logic verification at multiple levels (block, subsystem and full chip) and defines and develops scalable and reusable verification plans, test benches, and the verification environment
Job Summary
Performs functional logic verification at multiple levels (block, subsystem and full chip) and defines and develops scalable and reusable verification plans, test benches, and the verification environment.
Executes verification plans, runs emulation and system simulation models, analyzes power and performance, and debugs issues in the pre-silicon environment.
Collaborates with Architects, micro architects, RTL developers, post silicon, and physical design teams to improve verification of complex architectural and microarchitectural features.
Matching Summary
Performs functional logic verification at multiple levels (block, subsystem and full chip) and defines and develops scalable and reusable verification plans, test benches, and the verification environment.
Skills & Requirements
Must-have
Functional logic verification
Scalable and reusable verification plans
Test benches and verification environment
Constrained random verification methodologies
System Verilog
OVM/UVM
Nice-to-have
Collaborate with cross-functional teams
Security activities within test plans
FPGA architecture or prototyping
Formal verification experience
Key Requirements
3-5+ years of technical experience
BS, MS or PhD in Electrical or Computer Science Engineering