Dsp Or Serdes Rtl Sr Principal Digital Design Engineer

BETA CAE Systems International AG

San Jose, CA, USA
Base: $154,000 to $286,000; bonus/equity: not spec...
10+ years of serdes experience
Front-end coding and scripting
Digital design and verification
Join a dynamic and growing team of engineers developing high-speed PMA layer IP

Job Summary

  • Join a dynamic and growing team of engineers developing high-speed PMA layer IP.
  • The candidate will be responsible for front-end coding, scripting, and developing flows.
  • Excellent communication skills and self-motivation are essential for this role.

Matching Summary

Join a dynamic and growing team of engineers developing high-speed PMA layer IP.

Salary

Base: $154,000 to $286,000; Bonus/Equity: Not specified; Benefits: Paid vacation, 401(k), medical plans

Skills & Requirements

Must-have

  • 10+ years of SerDes experience
  • Front-end coding and scripting
  • Digital design and verification

Nice-to-have

  • Strong background in DSP
  • Experience with FPGA and emulation
  • Firmware development of embedded systems

Key Requirements

  • Substantial experience with Verilog
  • Understanding of digital architecture trade-offs
  • Experience with mixed-signal IP development

Work Rights

Not specified

Tailored Resume

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