2026 Campus - Soc Dft Engineer

NXP

Shanghai, China
Dft feature and architecture definition
Good knowledge of digital ic design
Good knowledge of verilog hdl
Participate in DFT feature and architecture definition for complex SOC

Job Summary

  • Participate in DFT feature and architecture definition for complex SOC.
  • Implement DFT logic/circuit including SCAN, Boundary SCAN, MBIST, Analog Macro test logic.
  • Generate DFT related timing constraints and support timing closure with backend engineer.

Matching Summary

Participate in DFT feature and architecture definition for complex SOC.

Skills & Requirements

Must-have

  • DFT feature and architecture definition
  • Good knowledge of digital IC design
  • Good knowledge of Verilog HDL

Nice-to-have

  • Good team player
  • Good English capabilities

Key Requirements

  • Bachelor or master degree
  • Good knowledge of DFT knowledge such as Scan/ATPG, MBIST and boundary scan

Work Rights

Not specified

Tailored Resume

Cover Letter