Sr. Ams Verification Engineer

Analog Devices

Cavite, Philippines
Systemverilog and uvm
Uvm-based verification environment development
Constrained random and assertion-based verification
As a Senior Analog Mixed-Signal Verification Engineer, you will lead verification planning and execution for complex digital and mixed-signal designs

Job Summary

  • As a Senior Analog Mixed-Signal Verification Engineer, you will lead verification planning and execution for complex digital and mixed-signal designs.
  • You will architect and implement comprehensive verification strategies for complex digital/mixed-signal designs and lead debug efforts for complex design issues.
  • At Analog Devices, you'll be part of a collaborative and innovative team that's shaping the future of technology, offering competitive compensation and benefits.

Matching Summary

As a Senior Analog Mixed-Signal Verification Engineer, you will lead verification planning and execution for complex digital and mixed-signal designs.

Skills & Requirements

Must-have

  • SystemVerilog and UVM
  • UVM-based verification environment development
  • constrained random and assertion-based verification
  • mixed-signal design principles
  • Python, Perl, TCL scripting

Nice-to-have

  • technical forums and customer interactions
  • continuous learning opportunities
  • shaping the future of technology

Key Requirements

  • 4-8 years of relevant experience
  • Bachelor's degree required, Master's preferred

Work Rights

Not specified

Tailored Resume

Cover Letter