Fpga Design - Principal Engineer / Lead Engineer / Senior Engineer / Engineer

ASTRI - Hong Kong Applied Science and Technology Research Institute Company Ltd

Hong Kong, HK
Competitive salary; performance-linked variable py...
On-site
Verilog rtl coding experience
Xilinx fpga development flow
Wireless communications phy knowledge
ASTRI is seeking professionals to develop high-performance wireless communications FPGA solutions for 5G/6G L1 Physical layer projects

Job Summary

  • ASTRI is seeking professionals to develop high-performance wireless communications FPGA solutions for 5G/6G L1 Physical layer projects.
  • The role involves performing RTL coding, synthesis, implementation, and speed & area optimization while collaborating with hardware and software engineers.
  • Candidates will benefit from a competitive salary, performance-linked variable pay, and comprehensive fringe benefits including medical insurance and MPF contributions.

Matching Summary

ASTRI is seeking professionals to develop high-performance wireless communications FPGA solutions for 5G/6G L1 Physical layer projects.

Salary

Competitive salary; Performance-linked variable pay; Paid leave, medical, insurance, MPF contribution

Skills & Requirements

Must-have

  • Verilog RTL coding experience
  • Xilinx FPGA development flow
  • Wireless communications PHY knowledge

Nice-to-have

  • Python or Tcl scripting skills
  • Experience with ORAN or WiFi standards
  • Background in 5G/6G standardization

Key Requirements

  • PhD, Master's, or Bachelor's in Engineering or Computer Science
  • Fresh graduates are eligible to apply
  • Knowledge of wireless communication standards like 5G/6G

Work Rights

Not specified

Tailored Resume

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