The role involves leading verification strategy and execution for complex SoCs with a hands-on approach
Job Summary
The role involves leading verification strategy and execution for complex SoCs with a hands-on approach.
The candidate will be responsible for developing, debugging, and running UVM based verification environments and driving DV closure on diverse IPs and subsystems.
The position requires collaboration with design teams and mentoring team members while ensuring compliance with functional safety and security requirements.
Matching Summary
The role involves leading verification strategy and execution for complex SoCs with a hands-on approach.
Skills & Requirements
Must-have
SoC-level verification strategy
ARM-based microcontrollers expertise
SystemVerilog and UVM proficiency
Low-power design verification
Experience with multiple interfaces
Gate-level and power-aware simulations
Functional safety and security compliance
Nice-to-have
Strong team player
Excellent communication skills
Mentoring and leadership
Fast-paced environment adaptability
Knowledge of Flash memory and security IPs
Familiarity with Analog IPs in microcontrollers
Key Requirements
10+ years in SoC/IP verification
Successful tape-outs of multiple SoCs
Bachelor’s or Master’s degree in Microelectronics or related fields