Soc Physical Design Timing Engineer

Intel Corporation

Bangalore, India
Hybrid
10+ years physical implementation experience
Sta and timing closure activities
Primetime tool proficiency
The candidate will be responsible for STA and timing closure activities of Intel SoCs and partitions

Job Summary

  • The candidate will be responsible for STA and timing closure activities of Intel SoCs and partitions.
  • This role requires hands-on experience with industry standard tools like Primetime and strong scripting skills in TCL, Perl, or Shell.
  • Candidates must possess a Bachelor's or Master's degree in Electrical/Electronics Engineering with over 10 years of relevant experience.

Matching Summary

The candidate will be responsible for STA and timing closure activities of Intel SoCs and partitions.

Skills & Requirements

Must-have

  • 10+ years Physical Implementation experience
  • STA and timing closure activities
  • Primetime tool proficiency
  • TCL Perl Shell scripting skills

Nice-to-have

  • Strong analytical problem solving skills
  • Self-motivated with initiative for improvements
  • Experience driving new methodologies
  • Ability to work in diverse team environment

Key Requirements

  • Bachelor or Master of Engineering degree
  • 10+ years of relevant experience
  • Skills in Physical Implementation and Timing Closure

Work Rights

Not specified

Tailored Resume

Cover Letter