Principal Verification Engineer

Altera

New Delhi, India
Fully remote
Systemverilog and uvm expertise
10+ years asic/fpga verification experience
Constrained-random test environment development
The role involves developing robust verification environments using SystemVerilog and UVM for FPGA acceleration projects

Job Summary

  • The role involves developing robust verification environments using SystemVerilog and UVM for FPGA acceleration projects.
  • Candidates must have over a decade of experience in ASIC or FPGA design verification with strong HDL skills.
  • The position requires defining comprehensive verification strategies and driving coverage closure through automation.

Matching Summary

The role involves developing robust verification environments using SystemVerilog and UVM for FPGA acceleration projects.

Skills & Requirements

Must-have

  • SystemVerilog and UVM expertise
  • 10+ years ASIC/FPGA verification experience
  • Constrained-random test environment development
  • Coverage-driven verification methodology
  • Python or Perl scripting skills

Nice-to-have

  • Familiarity with AMBA protocols like AXI
  • Experience with PCIe or Ethernet protocols
  • Strong analytical problem-solving abilities
  • Collaborative cross-functional team work

Key Requirements

  • Bachelor's or Master's degree in Electrical Engineering
  • 10+ years of experience in ASIC or FPGA verification
  • Proficiency in Verilog, VHDL, and SystemVerilog

Work Rights

Not specified

Tailored Resume

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