Job Summary

• Provide comprehensive DFT tool/flow/methodology support to address customer issues and challenges, ensuring successful tape-outs and maximum customer satisfaction.
• Drive quality improvements in ASIC DFT/DFM and ATPG validation methodology, capability/flow, and documentation for both block-level and SoC-level implementations.
• We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Matching Summary

Salary

Base: $122,440.00-232,190.00 USD; Bonus/Equity: stock bonuses; Benefits: health, retirement, and vacation

Skills & Requirements

Key Requirements

• 3+ years of experience with advanced CMOS processes (22nm and below)
• 3+ years of combined experience in ASIC DFT/DFM insertion and ATPG validation
• 2+ years of experience in scripting languages
• Bachelor's degree in Electrical Engineering, Computer Engineering, or STEM-related field
• US Citizenship required
• Ability to obtain US Government Security Clearance

Work Rights