Mixed Signal Logic Design Engineer

Intel

Penang, Malaysia
Hybrid
8+ years of rtl coding experience
Systemverilog implementation skills
Ddr phy ip integration knowledge
The role involves developing logic design and RTL coding for DDRPHY IP while defining architecture and microarchitecture features

Job Summary

  • The role involves developing logic design and RTL coding for DDRPHY IP while defining architecture and microarchitecture features.
  • Candidates must ensure design integrity by performing quality checks ranging from RTL to timing and power convergence.
  • The position requires strong communication skills to collaborate with verification, timing, and physical teams across cross-site partners.

Matching Summary

The role involves developing logic design and RTL coding for DDRPHY IP while defining architecture and microarchitecture features.

Skills & Requirements

Must-have

  • 8+ years of RTL coding experience
  • SystemVerilog implementation skills
  • DDR PHY IP integration knowledge
  • Static Timing Analysis proficiency
  • Clock Domain Crossing checking

Nice-to-have

  • Knowledge of Synthesis and Auto P&R
  • Experience with Primetime tools
  • Post-silicon testing background
  • Tcl/Perl/Python automation skills
  • Team coaching and training experience

Key Requirements

  • 8+ years of RTL coding or IP integration experience
  • Strong knowledge of analog circuits and mixed signal designs
  • Experience with industry standard high speed bus protocols

Work Rights

Not specified

Tailored Resume

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