Altera is driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure with cutting-edge FPGA, CPLD, and IP technologies
Job Summary
Altera is driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure with cutting-edge FPGA, CPLD, and IP technologies.
The role involves designing and optimizing mixed-signal and high-speed IPs, participating in architectural definition, and ensuring designs meet power, performance, area, and timing goals.
Candidates with at least 10 years of experience, proven expertise in SerDes and PHY design, and hands-on post-silicon validation are sought.
Matching Summary
Altera is driving innovation in high-speed connectivity, AI acceleration, and next-generation data infrastructure with cutting-edge FPGA, CPLD, and IP technologies.