RTL Design Engineer (ASIC/SOC)

HKM HR MANAGEMENT PTE. LTD.

Singapore
Master in electrical engineering
5 years rtl/soc experience
Verilog and systemverilog proficiency
Lead the RTL design, simulation, and verification processes to ensure robustness of ASIC and SoC products

Job Summary

  • Lead the RTL design, simulation, and verification processes to ensure robustness of ASIC and SoC products.
  • Collaborate closely with backend teams on coding, implementation, and synthesis to achieve successful tapeout.
  • Create and maintain reusable intellectual property blocks specifically tailored for AI and in-memory computing applications.

Matching Summary

Match Score: 85

Lead the RTL design, simulation, and verification processes to ensure robustness of ASIC and SoC products.

Skills & Requirements

Must-have

  • Master in Electrical Engineering
  • 5 years RTL/SoC experience
  • Verilog and SystemVerilog proficiency
  • VCS and Verdi tool expertise
  • AMBA APB and AXI protocol knowledge
  • Pre-layout and post-layout simulation

Nice-to-have

  • RISC or Arm core architecture familiarity
  • Mentoring junior engineers
  • Reusable IP creation for AI
  • Cross-functional collaboration skills
  • Post-Si testing support experience

Key Requirements

  • Minimum Master degree in Electrical Engineering
  • 5+ years working experience in digital design
  • Proficiency in industry-standard EDA tools

Work Rights

Not specified

Tailored Resume

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