Architect and implement UVM verification environments for AMD (Xilinx) FPGA/SoC designs
Job Summary
Architect and implement UVM verification environments for AMD (Xilinx) FPGA/SoC designs.
Develop verification plans with traceability to system and hardware requirements and author SystemVerilog Assertions (SVA).
Collaborate with design engineers on RTL reviews, bug resolution, and support hardware validation and board bring-up.
Matching Summary
Architect and implement UVM verification environments for AMD (Xilinx) FPGA/SoC designs.
Salary
Base: $123,000 - $193,000 USD; Bonus/Equity: Highly competitive equity grants; Benefits: Top-tier benefits including healthcare, income protection, generous time off
Skills & Requirements
Must-have
UVM-based methodology
SystemVerilog
object-oriented programming
AMD (Xilinx) platforms
coverage-driven verification
Nice-to-have
DO-254 compliance
avionics verification standards
safety-critical verification
formal verification tools
CDC verification tools
Key Requirements
Bachelor's degree in EE, CE, or related
2+ years of FPGA/ASIC verification experience
Proficient in SystemVerilog, UVM, SVA
Eligible to obtain U.S. Secret security clearance
Work Rights
Must hold or be eligible for U.S. Secret clearance