Asic Design Verification Manager

Micron Technology

Ip/block/subsystem verification
System verilog/uvm testbench development
Pcie5-6-7/nvme protocols
Responsible for overall IP/Block and Subsystem verification from Test plan creation, System Verilog/UVM testbench development to Sign-off

Job Summary

  • Responsible for overall IP/Block and Subsystem verification from Test plan creation, System Verilog/UVM testbench development to Sign-off.
  • Ability to lead and mentor a team of verification engineers.
  • Ensure first pass product through verification coverage and sign-off criteria.

Matching Summary

Responsible for overall IP/Block and Subsystem verification from Test plan creation, System Verilog/UVM testbench development to Sign-off.

Skills & Requirements

Must-have

  • IP/Block/Subsystem verification
  • System Verilog/UVM testbench development
  • PCIe5-6-7/NVMe protocols
  • RTL debugging
  • Functional coverage coding
  • Verilog and System Verilog languages

Nice-to-have

  • Lead and mentor verification engineers
  • Cross-functional and global teams
  • Familiarity with NAND
  • AI tools for application enhancement

Key Requirements

  • 10+ Years of experience
  • M.S./M.Tech, BS/BE (Electronics)
  • Proven track record of building Verification Plan
  • Experience with Scoreboard, Assertions, Code Coverage analysis

Work Rights

Not specified

Tailored Resume

Cover Letter