You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization
Job Summary
You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization.
Work closely with various teams such as physical design, RTL, DFT, tool/flow owners, and EDA vendors to improve physical design methodologies.
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.
Matching Summary
You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization.
Skills & Requirements
Must-have
RTL to GDS Implementation flow
Hierarchical floor planning
Timing closure and sign-off
Physical verification and equivalence checks
Power Integrity Analysis
Automation scripts within STA tools
TCL/SHELL/PERL/Python scripting
Nice-to-have
Creative solutions for implementation issues
Empathy and collaboration
Revolutionizing data and infrastructure
Key Requirements
13+ years ASIC engineering experience
Experience with sub 16/14/7/5/3nm technologies
Experience with large designs (>100M gates)
Bachelor's or Master's Degree in Electrical or Computer Engineering