Asic Engineer || Sdc || Design And Timing Constraints | Exp 8+ Years

Cisco UK

8+ years asic experience
Full-chip sdc development
Primetime or tempus sta tools
This role involves defining, designing, and verifying ASIC subsystems for Cisco's next-generation networking platforms

Job Summary

  • This role involves defining, designing, and verifying ASIC subsystems for Cisco's next-generation networking platforms.
  • The engineer will collaborate with front-end and back-end teams to refine design constraints and ensure seamless physical design closure.
  • Candidates must possess a deep understanding of timing constraints including clock groups, exceptions, and clock exclusivity.

Matching Summary

This role involves defining, designing, and verifying ASIC subsystems for Cisco's next-generation networking platforms.

Skills & Requirements

Must-have

  • 8+ years ASIC experience
  • Full-chip SDC development
  • PrimeTime or Tempus STA tools
  • Clocking diagram creation
  • Synopsys DC synthesis tools
  • Verilog/SystemVerilog programming

Nice-to-have

  • Timing Constraint Manager (TCM)
  • Conformal Constraint Designer (CCD)
  • Spyglass CDC and Glitch analysis
  • Formal Verification with Formality
  • Python, Perl, or TCL scripting
  • Block level RTL design experience

Key Requirements

  • Bachelor's degree plus 8 years experience
  • Master's degree plus 6 years experience
  • PhD plus 1 year experience
  • Experience with functional and test mode SDCs
  • Knowledge of async boundaries and clocking concepts

Work Rights

Not specified

Tailored Resume

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