Define and own the global DFT architecture, including Hierarchical Scan, Compressed ATPG, Memory BIST/Repair (BISR), Logic BIST, and IEEE 1687 (IJTAG) networks for multi-die or chiplet -based designs
Job Summary
Define and own the global DFT architecture, including Hierarchical Scan, Compressed ATPG, Memory BIST/Repair (BISR), Logic BIST, and IEEE 1687 (IJTAG) networks for multi-die or chiplet -based designs.
Develop advanced strategies for defect-oriented testing (Cell-aware, Slack-aware) and optimize pattern volumes to balance aggressive coverage targets with tester memory constraints.
Provide technical mentorship to junior and senior engineers and act as a consultant for verification and backend teams to resolve "bottleneck" timing or routing issues caused by DFT structures.
Matching Summary
Define and own the global DFT architecture, including Hierarchical Scan, Compressed ATPG, Memory BIST/Repair (BISR), Logic BIST, and IEEE 1687 (IJTAG) networks for multi-die or chiplet -based designs.
Skills & Requirements
Must-have
DFT architectures
ATPG/MBIST/LBIST strategies
scan compression architectures
hierarchical DFT
TCL and Python/Perl scripting
Nice-to-have
Automotive ASIL-D functional safety
Volume Diagnostics and Yield Learning
technical conferences participation
Key Requirements
8+ years of hands-on DFT experience
Bachelor’s, Master’s, in Electrical Engineering, Computer Engineering, or related fields
Expert-level proficiency with EDA suites (Synopsys, Cadence, Siemens/Mentor)
Demonstrated ability to solve timing closure issues