Staff Logic Design Engineer

Teledyne LeCroy

Milpitas, CA, US
$141,900.00-$189,200.000; not specified; not speci...
Verilog/systemverilog rtl design
Fpga development
Pcie protocol (gen4/gen5/gen6)
Join a dynamic team that develops leading edge test and measurement products

Job Summary

  • Join a dynamic team that develops leading edge test and measurement products.
  • Architect and implement high-performance digital logic for protocol capture, analysis, and emulation.
  • Collaborate with cross-functional teams to deliver industry-leading solutions.

Matching Summary

Join a dynamic team that develops leading edge test and measurement products.

Salary

$141,900.00-$189,200.000; Not specified; Not specified

Skills & Requirements

Must-have

  • Verilog/SystemVerilog RTL design
  • FPGA development
  • PCIe protocol (Gen4/Gen5/Gen6)
  • Timing closure
  • UVM testbenches

Nice-to-have

  • Protocol analyzers experience
  • Hardware/software co-design
  • Scripting for automation
  • Test & measurement environments

Key Requirements

  • 7+ years of digital logic design experience
  • BS in EE, CS or Computer Engineering
  • Experience with PCIe, CXL, NVMe, USB, SAS, SATA
  • Hands-on with FPGA toolchains
  • Knowledge of UVM

Work Rights

Not specified

Tailored Resume

Cover Letter