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Cisco UK is seeking a Senior Staff Timing Engineer to join their Test Timing Engineering team in Armenia. The role focuses on developing and validating timing constraints for advanced chip designs, requiring extensive experience in Static Timing Analysis and strong programming skills.
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Job Summary
Own the creation and validation of timing constraints at block, sub-chip, and full-chip levels in various test modes.
Develop and enhance methodologies, guidelines, and checklists to streamline static timing analysis (STA) workflows.
Collaborate with cross-functional teams to resolve timing and design flow issues, accelerating project execution.
Matching Summary
Match Score: 75
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Cisco UK is seeking a Senior Staff Timing Engineer to join their Test Timing Engineering team in Armenia. The role focuses on developing and validating timing constraints for advanced chip designs, requiring extensive experience in Static Timing Analysis and strong programming skills.
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Skills & Requirements
Must-have
Static Timing Analysis (STA)
SDC flows and validation
timing constraints development
scripting languages (Perl, TCL, Python)
Nice-to-have
debugging timing constraints for DFT
collaboration within cross-functional teams
Synopsys Fusion Compiler experience
Key Requirements
Bachelor's degree with 8+ years experience or Master's degree with 6+ years experience
Developing block/full-chip SDC in test modes
Proficiency in Static Timing Analysis (STA)
Programming proficiency in at least two scripting languages