Asic Physical Design Cad, Timing Constraint And Analysis

NVIDIA

Master's or phd in electrical engineering
2+ years physical design implementation experience
Advanced proficiency in synopsys primetime or cadence tempus
The role involves developing timing analysis methodologies and implementing flow automation for large-scale, high-speed semicustom chips

Job Summary

  • The role involves developing timing analysis methodologies and implementing flow automation for large-scale, high-speed semicustom chips.
  • Candidates will establish methodologies for timing constraints and SDC release, including automatic constraint generation and linting.
  • Engineers will collaborate with EDA vendors to enhance commercial timing signoff tools and work on the most advanced process technologies.

Matching Summary

The role involves developing timing analysis methodologies and implementing flow automation for large-scale, high-speed semicustom chips.

Skills & Requirements

Must-have

  • Master's or PhD in Electrical Engineering
  • 2+ years physical design implementation experience
  • Advanced proficiency in Synopsys PrimeTime or Cadence Tempus
  • Expertise in timing constraints definition and SDC release
  • Proficiency in Perl, TCL, Python, or C++ scripting

Nice-to-have

  • Experience in flow development or automation
  • Knowledge of RTL simulation and validation
  • Collaboration with cross-functional ASIC/P&R/DFT teams

Key Requirements

  • Master's or PhD degree required
  • Minimum 2 years hands-on experience
  • Strong STA principles and signoff knowledge

Work Rights

Not specified

Tailored Resume

Cover Letter