Senior Staff Manager

Marvell Technology

Not specified; not specified; competitive compensa...
12-18 years vlsi design experience
Verilog/systemverilog expertise
Soc interconnect protocols noc axi ahb
This role involves defining micro-architecture for complex blocks and subsystems while ensuring they meet rigorous performance, power, and area targets

Job Summary

  • This role involves defining micro-architecture for complex blocks and subsystems while ensuring they meet rigorous performance, power, and area targets.
  • The successful candidate will manage a team of 10-12 engineers, fostering a culture of innovation while providing hands-on technical guidance.
  • Marvell offers competitive compensation, great benefits, and an environment of shared collaboration, transparency, and inclusivity.

Matching Summary

This role involves defining micro-architecture for complex blocks and subsystems while ensuring they meet rigorous performance, power, and area targets.

Salary

Not specified; Not specified; Competitive compensation and great benefits

Skills & Requirements

Must-have

  • 12-18 years VLSI design experience
  • Verilog/SystemVerilog expertise
  • SoC interconnect protocols NoC AXI AHB
  • Clocking reset architectures CDC/RDC analysis
  • Synopsys or Cadence EDA tools proficiency
  • Manage team of 10-12 engineers
  • Silicon lifecycle oversight RTL synthesis

Nice-to-have

  • Strong communication and brokering skills
  • Culture of innovation mentorship
  • Experience with big tech customers
  • Process improvement best practices

Key Requirements

  • Bachelor's or Master's degree in Electrical or Computer Engineering
  • 3-5 years formal management or technical lead capacity
  • Eligibility to access export-controlled information under US law

Work Rights

Must be eligible to access export-controlled information as defined under applicable law

Tailored Resume

Cover Letter