Asic Engineering Technical Leader

Cisco

Bangalore, India
Hardware design-for-test (dft)
Jtag protocols
Scan and bist architectures
You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases

Job Summary

  • You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases.
  • Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models.
  • At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era.

Matching Summary

You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases.

Skills & Requirements

Must-have

  • Hardware Design-for-Test (DFT)
  • Jtag protocols
  • Scan and BIST architectures
  • ATPG and EDA tools

Nice-to-have

  • Verilog design experience
  • DFT CAD development
  • Scripting skills in Tcl, Python/Perl

Key Requirements

  • Bachelor's or Master’s Degree in Electrical or Computer Engineering
  • At least 10 years of experience
  • Post-silicon validation and debug experience

Work Rights

Not specified

Tailored Resume

Cover Letter