Mixed Signal Logic Verification Engineer

Intel

Bangalore, India
Hybrid
11-15 years asic verification experience
System verilog and uvm expertise
Mixed signal ip verification strategy
This role requires a Senior or Staff engineer with 11-15 years of experience to drive complex SoC and ASIC verification strategies

Job Summary

  • This role requires a Senior or Staff engineer with 11-15 years of experience to drive complex SoC and ASIC verification strategies.
  • The successful candidate will lead the development of advanced test benches using System Verilog and UVM while ensuring coverage closure.
  • Candidates must possess expert-level debugging capabilities for RTL, gate-level simulations, and post-silicon failures within mixed signal designs.

Matching Summary

This role requires a Senior or Staff engineer with 11-15 years of experience to drive complex SoC and ASIC verification strategies.

Skills & Requirements

Must-have

  • 11-15 years ASIC verification experience
  • System Verilog and UVM expertise
  • Mixed signal IP verification strategy
  • JTAG/APB protocol proficiency
  • Synopsys VCS and Cadence Xcelium tools

Nice-to-have

  • Mentoring junior engineers
  • Formal verification methods
  • Python scripting for automation
  • Root cause analysis skills
  • Collaboration with architects

Key Requirements

  • 11-15 years of ASIC/SoC verification experience
  • B.E/B.Tech or M.E/M.Tech/MS in Electronics/VLSI
  • Expert knowledge of System Verilog and UVM

Work Rights

Not specified

Tailored Resume

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