Principal Dft Engineer

NXP Semiconductors

Multiple Locations
Dft scan architecture
Jtag
Memory bist
Architect, implement, and validate in-vehicle networking devices as part of NXP’s Automotive grade products

Job Summary

  • Architect, implement, and validate in-vehicle networking devices as part of NXP’s Automotive grade products.
  • Responsible for advanced test strategies and implementation, verification and validation of pre/post tapeout of DFT features, overall test coverage improvements.
  • Coordinate with physical design and test engineering teams to ensure timing closure and that test patterns are operational immediately upon silicon arrival.

Matching Summary

Architect, implement, and validate in-vehicle networking devices as part of NXP’s Automotive grade products.

Skills & Requirements

Must-have

  • DFT Scan Architecture
  • JTAG
  • Memory BIST
  • Logic BIST
  • ATPG pattern generation
  • post-silicon validation
  • Verilog or SystemVerilog HDL

Nice-to-have

  • Automate test insertion flows
  • parse coverage reports

Key Requirements

  • 10+ years industry experience
  • B.S./M.S. Electrical/Computer Engineering
  • SoC DFT implementation
  • static timing closure
  • test coverage analysis and improvement
  • silicon bring-up on ATE

Work Rights

Not specified

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