Asic/fpga Design And Verification Engineer - (lead, Senior, Or Principal)

Boeing Co

Albuquerque, NM, USA
Base: $136,850 - $266,800 (level dependent); bonus...
Not specified (assumed to be onsite based on company culture and project needs)
9+ years asic/fpga experience
Systemverilog hardware verification
Bachelor's degree in engineering
Boeing is seeking multiple ASIC/FPGA Design and Verification Engineers at various levels (Lead, Senior, Principal) to join their Electronic Products team in Albuquerque, NM. The role involves leading the design and verification of complex ASICs and FPGAs for various aerospace applications, emphasizing collaboration and innovation in high-performance embedded systems

Job Summary

  • This role involves developing state-of-the-art digital ICs and SoCs for critical Boeing programs including satellite constellations and commercial avionics.
  • Engineers will lead FPGA/ASIC designs, manage team execution, and collaborate with cross-functional teams to define system requirements and ensure hardware-software compatibility.
  • The position offers competitive compensation ranging from $136,850 to $266,800 depending on the level, along with relocation assistance and comprehensive benefits.

Matching Summary

Match Score: 85

Boeing is seeking multiple ASIC/FPGA Design and Verification Engineers at various levels (Lead, Senior, Principal) to join their Electronic Products team in Albuquerque, NM. The role involves leading the design and verification of complex ASICs and FPGAs for various aerospace applications, emphasizing collaboration and innovation in high-performance embedded systems.

Salary

Base: $136,850 - $266,800 (Level dependent); Bonus/Equity: Variable compensation opportunities; Benefits: Health insurance, retirement plans, paid time off

Skills & Requirements

Must-have

  • 9+ years ASIC/FPGA experience
  • SystemVerilog hardware verification
  • Bachelor's degree in Engineering
  • US Citizenship required
  • Hardware integration and testing

Nice-to-have

  • Palladium hardware emulator proficiency
  • Space-based radiation mitigation knowledge
  • UVM testbench development skills
  • High-speed Serdes interface experience
  • Mentoring junior engineers

Key Requirements

  • Bachelor of Science in Engineering or related field
  • 9+ years ASIC/FPGA design or verification experience
  • Must possess US Citizenship for security clearance
  • Ability to obtain U.S. Secret Clearance post-start
  • Experience with SystemVerilog and production design delivery

Work Rights

Must have US citizenship

Tailored Resume

Cover Letter