Not specified (assumed hybrid based on internship nature)
Systemc modeling experience
Cadence xcelium simulation tools
Rtl co-simulation skills
Cadence is seeking an Embedded System Architect Intern to develop TLM models for Secure Element components and validate XIP execution mode. The role focuses on enhancing system performance and reliability through SystemC modeling, RTL co-simulation, and PPA analysis
Job Summary
The intern will develop Transaction Level Modeling (TLM) for Secure Element components including CPU, RAM, and Flash.
Responsibilities include implementing and validating the XIP execution mode within a SystemC model environment.
The role requires integrating SystemC and RTL co-simulation under Cadence Xcelium to analyze performance, power, and area metrics.
Matching Summary
Match Score: 85
Cadence is seeking an Embedded System Architect Intern to develop TLM models for Secure Element components and validate XIP execution mode. The role focuses on enhancing system performance and reliability through SystemC modeling, RTL co-simulation, and PPA analysis.
Skills & Requirements
Must-have
SystemC modeling experience
Cadence Xcelium simulation tools
RTL co-simulation skills
Python or C++ proficiency
PPA analysis capabilities
Nice-to-have
Knowledge of cryptography
Hardware design architecture understanding
Firmware scenario experience
Technical report writing
English language fluency
Key Requirements
Degree in Electronics, Microelectronics, or Computer Science