Sr Principal Verification Engineer

Cadence

Multiple Locations
Functional verification (formal/simulation/uvm)
Debugging pre-silicon failures
Industry standard eda tools
Contribute to the application of machine learning techniques aimed at streamlining traditional pre-silicon functional verification methodologies like formal verification and UVM

Job Summary

  • Contribute to the application of machine learning techniques aimed at streamlining traditional pre-silicon functional verification methodologies like formal verification and UVM.
  • Develop agentic AI solutions using LLMs and latest ML technologies to accelerate pre-silicon Design Verification process.
  • Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.

Matching Summary

Contribute to the application of machine learning techniques aimed at streamlining traditional pre-silicon functional verification methodologies like formal verification and UVM.

Skills & Requirements

Must-have

  • Functional verification (formal/simulation/UVM)
  • Debugging pre-silicon failures
  • Industry standard EDA tools
  • Verilog, System Verilog, Python
  • AI enhanced EDA tools

Nice-to-have

  • Results driven
  • Passion for AI innovation
  • Thrive in team-oriented environment
  • Proactive problem solving
  • Continuous learning and innovation

Key Requirements

  • 12-15+ years ASIC verification experience
  • Bachelor's or Master's degree
  • Experience with Jasper, Xcelium, IMC
  • Exposure to LLMs and ML technologies

Work Rights

Not specified

Tailored Resume

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